The present invention relates to an information processing apparatus and, more particularly, to directory management of an address conversion table upon a processor failure in a multiprocessor arrangement.
A conventional information processing apparatus of this type has an arrangement as shown in a block diagram of FIG. 2. In this arrangement, in order to allow an arithmetic operation processor 24 to access a main memory unit 1, the arithmetic operation processor 24 sends a request code, a logic address, and a processor number (hereinafter 'No.") through a line 2401 and sets them in a register 3 via a selector 2.
The register 3 sends the request code to a control unit 20 through a line 305 and sends a partial space No. of the logic address and the processor No. to comparing units 12 to 15 through a line 301. The comparing units 12 to 15 compare the partial space No. from the line 301 with partial space Nos. of directories 4 to 7, respectively, and compare the processor No. from the line 301 with processor numbers (hereinafter "Nos.") of the directories 4 to 7, respectively. If any of the comparing units 12 to 15 finds a coincidence, it reports this coincidence to the control unit through a corresponding one of lines 1201, 1301, 1401, and 1501. The directory 4 is paired to an address converting unit 16, and the directories 5 to 7 are paired to address converting units 17 to 19, respectively. As shown in FIG. 3, each of the directories 4 to 7 holds four bits of processor No. in one-to-one correspondence to arithmetic operation processors 24 to 27 and a partial space No. corresponding to the partial space No. of the logic address of the register 3. This logic address has 30 bits constituted by 10 bits of a partial space No., 10 bits of a page No., and 10 bits of an intrapage address, as shown in FIG. 4.
The page No. of the logic address from the register 3 is supplied to the address converting units 16 to 19 through a line 302. The address converting units 16 to 19 read out addresses from corresponding tables and send the readout addresses to a selector 21 through lines 1601, 1701, 1801, and 1901.
When the control unit 20 receives the request code from the register 3 through the line 305 and determines access to the memory unit 1, it checks the coincidence results from the line 1201, 1301, 1401, and 1501. The control unit 20 controls the selector 21 through a line 2001 so as to select an address of one of the address converting units 16 to 19 corresponding to one of the comparing units 12 to 15, which outputs the coincidence, and sets the address in a register 22 through a line 2101. At the same time, the control unit 20 sets the intrapage address of the register 3 in the register 22 through a line 304. As a result, since the logic address of the register 3 is set as a physical address in the register 22, access to the memory unit 1 is performed through a line 2201.
Registration of address conversion tables in the directories 4 to 7 and the address converting units 16 to 19 will be described below.
In order to load an address conversion table having partial space No. "20" from the arithmetic operation processor 25, the selector 2 selects a processor No., the partial space No. "20", and a logic address together with a request code from the arithmetic operation processor 25 through a line 2501 and sets them in the register 3. The format of the register 3 is shown in FIG. 5. Referring to FIG. 5, this partial space No. indicates a partial space No. located in the same bit position as that of the partial space No. but to be registered in an address conversion table and is different from a current logic address. The current logic address indicates a read start address of an address conversion table to be registered from the memory unit 1 into the address converting units 16 to 19. In access to the memory unit 1 at this time, no address conversion is performed. Therefore, as an address to be used in access to the memory unit 1 for an address conversion table read operation, the logic address of the register 3 is directly set in the register 22 such that the partial space No. and the page No. of the logic address are selected by the selector 21 through the line 303 and set in the register 22 and the intrapage address of the logic address is set in the register 22 through the line 304, thereby reading out the address conversion table from the memory unit 1. In accordance with the format of the logic address, information of 1,024 pages corresponding to 10 bits of the page No. is read out for each partial space from the memory unit 1. All of these addresses are generated on the arithmetic processor side to constantly set only the logic address in the register 3.
When the control unit 20 determines in accordance with the request code from the register 3 that registration processing of an address conversion table into the address converting units 16 to 19 is to be performed, it causes the comparing units 12 to 15 to check whether any one of the directories 4 to 7 is nonused. The comparing unit 12 has an arrangement as shown in FIG. 6, and each of the comparing units 13 to 15 has the same arrangement. Referring to FIG. 6, the controller 20 controls a selector 1210 to select "0" and compares "0" with a processor No. from the directory 4. A comparator 1211 is used to check a coincidence between the processor No. of the register 3 and that of the directory 4. In this case, the coincidence between the value "0" from the selector 1210 and the processor No. from the directory 4 indicates that all bits (bits 0 to 3 shown in FIG. 3) of the processor No. from the directory 4 are "0"s and the directory 4 is nonused. The result from the comparator 1211 is selected by a selector 1214 and supplied to the control unit 20 through the line 1201. Note that a comparator 1212 is used to check a coincidence between the partial space No. of the logic address of the register 3 and that of the directory 4 in a normal access mode to the memory unit 1. In this case, the results of the comparators 1211 and 1212 are ANDed by an AND gate 1213, and the resultant logical product is selected by the selector 1214 and supplied to the line 1201. The control unit 20 designates the same processing for the comparing units 13 to 15 and receives the results through the lines 1301, 1401, and 1501. In this case, assume that the directory 4 is nonused.
When the control unit 20 determines through the line 1201 that the directory 4 is nonused, it sets the processor No. (in this case, "0100" is set because the request is output from the arithmetic operation processor 25) and the partial space No. ("0000010100" is set as "20" of bits 20 to 29 shown in FIG. 5) of the register 3 in the directory 4. In addition, the address conversion table read out from the memory unit 1 is set in a register 8 through the line 101. The register 8 receives address conversion table information from the memory unit 1 in each machine cycle and sends the information to the address converting unit 16.
The address converting unit 16 has an arrangement as shown in FIG. 7. When data is set in the register 8, "0" is set in a count register 1610. The value "0" is selected by a selector 1611 and supplied as a write address to an address conversion table 1612, thereby writing the address conversion table information from the register 8. A value incremented by "1" is set in the count register 1610 in each machine cycle.
The address converting units 17 to 19 have the same arrangement as that of the address converting unit 16.
Deletion of registration from the directories 4 to 7 and the address converting units 16 to 19 will be described below. The deletion as processing is performed by resetting the processor Nos. of the directories 4 to 7. Assuming that the processor Nos. and the partial space Nos. of the directories 4, 5, 6, and 7 are "1000" "0000000001", "1000" and "0000001111", "0010" and "0000000001", and "0001" and "0000000001", respectively, an operation of clearing an address converting unit having the partial space No. "0000000001" from the arithmetic operation processor 24 will be described below.
The arithmetic operation processor 24 sets a request code, a partial space No., and a processor No. in bits 0 to 29 of the register 3 via the selector 2 through the line 2401. When the register 3 sends an instruction code to the control unit 20, the control unit 20 sends the processor No. "1000" and the partial space No. "0000000001" to the comparators 12 to 15 through the line 301 in order to delete a table of a corresponding one of the address converting units 16 to 19, i.e., to delete the processor No. from a corresponding one of the directories 4 to 7. The comparators 12 to 15 check whether the processor No. and the partial space No. from the line 301 coincide with the processor Nos. and the partial space Nos. of the directories 4 to 7, respectively. In this case, since a coincidence is obtained with respect to the contents of the directory 4, this coincidence is reported through the line 1201. Therefore, the control unit 20 sets "0000" as the processor No. of the directory 4 and ends the processing.
In the above conventional information processing apparatus, each arithmetic operation processor loads a corresponding necessary address conversion table into an address converting unit and issues an instruction for deleting the table when the table becomes unnecessary. Therefore, if an arithmetic operation processor using an address conversion table goes down by abnormality without clearing the address conversion table, then an address conversion table in use cannot be cleared and is left occupied. As a result, part of the address conversion tables become unusable, all of which could have been used originally. This causes a decrease in the use efficiency of the address conversion tables, a frequent need to perform a process for registration of the remaining address conversion tables, increased overhead, and an overall reduction in system performance.